Memory devices are driven by new applications and the requirements of the future. Advancements in the fields of computers and communications will require large quantities of each of the species of memories. For example, computer interfaces will be operated by speech processing or vision processing, and other communication interfaces, all of which require a significant amount of memory. Memory technology will continue to move in the direction of increased numbers of devices in a wafer. Read only memory (ROM) devices include ROM cells for coding data and a peripheral controlling devices to control the operation of the cells. Each bit of data is stored in a cell, which is a single n-channel transistor or ROM cell. As is well known in the art, the programming of the ROM is executed by controlling a threshold voltage of the MOS transistors constructing the memory cell by the implantation of dopant.
In general, a mask ROM includes devices with different threshold voltages. A type of device is formed in an active area and another type of device with a threshold voltage mask is formed in another active area during the process. In MOS transistors for a mask ROM, the threshold voltages of the channel regions under the gates are set to the same before data writing. Thereafter, ions are selectively implanted into determined regions to differentiate the threshold voltages thereof for data writing. One of the methods that involves differentiating the threshold voltages is achieved by ion implantation of some of the transistor gates. This method raises the threshold voltage of the n-channel device by doping boron with a heavy dose. The prior art relating to the ROM can be seen in U.S. Pat. No. 5,372,961 and U.S. Pat. No. 5,538,906 disclosed by Noda and Aoki, respectively. The process of ion implantation having high dose boron through the sacrificial oxide or the polysilicon gate into the substrate is widely used to fabricate the normally off mask ROM devices.
However, the high dose boron implantation results in a lower junction breakdown voltage of the coded MOS and, more importantly, to a very high leakage current between the adjacent bit lines. As mentioned in U.S. Pat. No. 5,597,753 disclosed by Sheu, the high leakage current results in very high standby current. Another problem occurs with the ROM code implantation. As is known in the art, after the code implantation is carried out, a thermal process is used to activate the implanted dopant which will cause counter doping of the adjacent bit lines, thereby increasing the bit line resistance and substantially degrading the performance of the ROM devices. One prior art reference which teaches the reduction of the bit line resistance is disclosed by Hong in U.S. Pat. No. 5,571,739.